Method and circuit for shortcircuiting data transfer lines and semiconductor memory device having the circuit

ABSTRACT

There is provided a method of controlling data transmission lines of a semiconductor memory device which has a first pair of data transmission lines to which a sense amplifier and memory cells are connected, and a second pair of data transmission lines to which a read circuit and a write circuit are connected at an end of the second pair of the data transmission lines, which is connected to the first pair of data transmission lines via a column gate. The method includes a) shortcircuiting the second pair of data transmission lines for a first period when a read operation is carried out, and b) shortcircuiting the second pair of data transmission lines for a second period when a write operation is carried out, the second period being shorter than the first period.

BACKGROUND THE INVENTION

1. Field of the Invention

The present invention generally relates to a method and circuit forshortcircuiting a pair of data transfer lines of a semiconductor memorydevice in which complementary data signals are transmitted over the pairof data transfer lines in order to write data in a memory cell array orread data therefrom.

A DRAM (Dynamic Random Access Memory) device is known as such asemiconductor memory device in which complementary read or write datasignals are transmitted over a pair of transfer lines to which aplurality of rows of memory cells (such lines are referred to as globaldata transfer lines) are connected via local data transfer lines.Usually, such a pair of global data transfer lines, which functions as aglobal data bus, is connected together (shortcircuited) in order toprecharge the pair of global data transfer lines and thus speed up theoperation of the device. It is necessary to take into consideration atiming at which the pair of global data transfer lines is released fromthe precharged state. This consideration is important particularly forhigh-speed memory devices such as synchronous DRAM devices (hereinafterreferred to as SDRAM devices) and asynchronous DRAM devices needed tooperate with an operation cycle of 100 MHz or higher.

SUMMARY OF THE INVENTION

It is an object of the present invention to provide a method and circuitfor shortcircuiting a pair of data transfer lines which makes itpossible to speed up the read and write operations of a semiconductormemory device.

This object of the present invention is achieved by a method ofcontrolling data transmission lines of a semiconductor memory devicewhich has a first pair of data transmission lines to which a senseamplifier and memory cells are connected, and a second pair of datatransmission lines to which a read circuit and a write circuit areconnected at an end of the second pair of the data transmission lines,which is connected to the first pair of data transmission lines via acolumn gate, the method comprising: a) shortcircuiting the second pairof data transmission lines for a first period when a read operation iscarried out; and b) shortcircuiting the second pair of data transmissionlines for a second period when a write operation is carried out, thesecond period being shorter than the first period.

The above object of the present invention is also achieved by asemiconductor device comprising: memory cells; a sense amplifier; afirst pair of data transmission lines to which the sense amplifier andmemory cells are connected; a second pair of data transmission lines towhich a read circuit and a write circuit are connected at an end of thesecond pair of the data transmission lines, which is connected to thefirst pair of data transmission lines via a column gate; ashortcircuiting element which can shortcircuit the second pair of datatransmission lines; and a first control circuit which controls theshortcircuiting element so that the second pair of data transmissionlines is shortcircuited for a first period when a read operation iscarried out, and the second pair of data transmission lines isshortcircuited for a second period when a write operation is carriedout, the second period being shorter than the first period.

The second pair of data transmission lines may comprise: a third pair ofdata transmission lines to which the first pair of data transmissionlines is connected; and a fourth pair of data transmission lines towhich the read circuit and the write circuit are connected, the fourthpart of data transmission lines being coupled to the third pair of datatransmission lines via a switch circuit.

The semiconductor device may further comprise a precharging circuitwhich supplies a precharge voltage to the second pair of datatransmission lines.

The precharging circuit may supply the precharge voltage to the secondpair of data transmission lines while the second pair of datatransmission lines is being shortcircuited, and does not supply theprecharge voltage thereto when the second pair of data transmissionlines is not shortcircuited.

The first control circuit may control the shortcircuiting element sothat a timing at which the second pair of data transmission lines isshortcircuited substantially coincides with a first signal defining anoperation timing in the read and write operations, and a timing at whichthe second pair of data transmission lines is released from ashortcircuited state in the write operation is earlier, with respect tothe first signal, than a timing at which the second pair of datatransmission lines is released from the shortcircuited state in the readoperation.

The first control circuit may control the shortcircuiting element sothat the second pair of data transmission lines is released from ashortcircuited state in the read operation after the second pair of datatransmission lines is precharged to the precharge voltage.

The first control circuit may control the shortcircuiting element sothat the second pair of data transmission lines is released from ashortcircuited state in the write operation before the second pair ofdata transmission lines is precharged to the precharge voltage.

The write circuit may have a driving capability of setting the secondpair of data transmission lines to the precharge voltage faster than theprecharging circuit precharges the second pair of data transmissionlines to the precharge voltage when the write circuit invertscomplementary signals on the second pair of data transmission lines.

The first control circuit may comprise: a second control circuit whichcontrols timings at which the second pair of data transmission lines isshortcircuited and released from a shortcircuited state in the writeoperation; a third control circuit which controls timings at which thesecond pair of data transmission lines is shortcircuited and releasedfrom the shortcircuited state in the read operation; and a fourthcontrol circuit which controls a timing at which the shortcircuitingelement shortcircuits the second pair of data transmission lines on thebasis of output signals of the second and third control circuits.

The second control circuit may comprise a first NAND circuit whichperforms a NAND operation on a first signal defining an operation timingand a second signal indicating whether an operation mode of thesemiconductor memory device is the write operation or the readoperation. The third control circuit may comprise a first delay circuitdelaying the first

signal, and a second NAND circuit performing a NAND operation on anoutput signal of the first delay circuit and the first signal. Thefourth control circuit may comprise a third NAND circuit performing aNAND operation on an output signal of the second control circuit and anoutput signal of the third control circuit, and a first inverting delaycircuit which inverts and delays an output signal of the third NANDcircuit.

The first signal may be a signal synchronized with an external clockapplied to the semiconductor memory device.

The semiconductor memory device may further comprise a second controlcircuit which controls enabling of the write circuit which outputs datato the second pair of data transmission lines at almost the same time asthe second pair of data transmission lines is released from ashortcircuited state.

The second control circuit may control the write circuit on the basis ofa first signal defining an operation timing and a second signalindicating whether an operation mode of the semiconductor memory deviceis the write operation or the read operation.

The second control circuit may comprise: a first inverting circuit whichinverts the first signal; a second inverting circuit which inverts thesecond signal; a first NOR circuit which performs a NOR operation onoutput signals of the first and second inverting circuits; and a firstdelay circuit which delays an output signal of the first NOR circuit.

The semiconductor memory device may further comprise a second controlcircuit which controls enabling of the write circuit on the basis of afirst signal defining an operation timing and a second signal indicatingwhether an operation mode of the semiconductor memory device is thewrite operation or the read operation.

The second control circuit may comprise: a first inverting circuit whichinverts the first signal; a first NOR circuit which performs a NORoperation on an output signal of the first inverting circuit and thesecond signal; and a first delay circuit which delays an output signalof the first NOR circuit.

The semiconductor memory device may further comprise a second controlcircuit which delays the first signal to generate a third signal used tocontrol timings at which the column gate is selected and released from aselected state at respective timings which are common to the readoperation and the write operation.

The semiconductor memory device may further comprise: a second controlcircuit which controls timings at which a column is selected andreleased from a selected state in the read and write operations; and athird control circuit which controls timings at which the column gate isselected and released from the selected state, wherein the timing atwhich the column gate is selected in the write operation lags behind thetiming at which the column gate is selected in the read operation, andthe timing at which the column gate is released from the selected statein the read operation substantially coincides with the timing at whichthe column gate is released from the selected state in the writeoperation.

The second control circuit may comprise: a first invention circuit whichinverts a first signal defining an operation timing; a first invertingdelay circuit which inverts and delays an output signal of the firstinverting circuit; a first NAND circuit which performs a NAND operationon a second signal indicating whether an operation mode of thesemiconductor memory device is the write operation or the read operationand an output signal of the first inverting circuit; and a first delaycircuit delays an output signal of the first NAND circuit. The thirdcontrol circuit may comprise: a second NAND circuit which performs aNAND operation on an output signal of the first inverting delay circuitand an output signal of the first delay circuit; and a second invertingcircuit which inverts an output signal of the second NAND circuit.

The semiconductor memory device may further comprise: a second controlcircuit which controls timings at which a column is selected andreleased from a selected state in the read operation; a third controlcircuit which controls timing at which a column is selected and releasedfrom the selected state in the write operation; a fourth control circuitwhich generates, from output signals of the second and third controlcircuits, a third signal which controls timings at which the column gateis selected and released from the selected state; and a fifth controlcircuit which controls the second control circuit. The timings at whichthe column gate is selected and released from the selected state in thewrite operation lag behind the timings at which the column gate isselected and released from the selected state in the read operation.

The second control circuit may comprise: a first inverting circuit whichinverts a first signal defining an operation timing; a first NANDcircuit which performs a NAND operation on an output signal of the firstinverting circuit and an output signal of the fifth control circuit; anda first delay circuit which delays an output signal of the first NANDcircuit. The third control circuit may comprise: a second NAND circuitwhich performs a NAND operation on a second signal indicating whether anoperation mode of the semiconductor memory device is the write operationor the read operation and an output signal of the first invertingcircuit; and a second delay circuit which delays an output signal of thesecond NAND circuit. The fourth control circuit may comprise: a thirdNAND circuit which performs a NAND operation on output signals of thesecond and third control circuits; and a second inverting circuit whichinverts an output signal of the third NAND circuits. The fifth controlcircuits may comprise: a third delay circuit which delays the secondsignal; and a fourth NAND circuit which performs a NAND operation on anoutput signal of the third delay circuit and the second signal.

BRIEF DESCRIPTION OF THE DRAWINGS

Other objects, features and advantages of the present invention willbecome more apparent from the following detailed description when readin conjunction with the accompanying drawings, in which:

FIG. 1 is a block diagram of a SDRAM device related to the presentinvention;

FIG. 2 is a circuit diagram of a memory cell shown in FIG. 1;

FIG. 3 is a circuit diagram of a sense amplifier shown in FIG. 1;

FIG. 4 is a circuit diagram of column gates shown in FIG. 1;

FIG. 5 is a circuit diagram of a sense buffer 40 shown in FIG. 1;

FIG. 6 is a circuit diagram of a write amplifier shown in FIG. 1;

FIGS. 7A and 7B are waveform diagrams of a read operation of the SDRAMdevice shown in FIG. 1;

FIGS. 8A and 8B are waveform diagrams of a write operation of the SDRAMdevice shown in FIG. 1;

FIG. 9 is a block diagram of a SDRAM device according to embodiments ofthe present invention;

FIG. 10 is a block diagram of a control circuit shown in FIG. 9;

FIGS. 11A and 11B are waveform diagrams of an operation of the SDRAMdevice according to a first embodiment of the present invention;

FIGS. 12A, 12B, 12C, 12D and 12E are waveform diagrams of the results ofa simulation of the operation of the SDRAM device according to the firstembodiment of the present invention;

FIG. 13 is a block diagram of a control circuit provided in an SDRAMdevice according to a second embodiment of the present invention;

FIGS. 14A and 14B are waveform diagrams of an operation of the secondembodiment of the present invention;

FIG. 15 is a block diagram of a control circuit provided in an SDRAMdevice according to a third embodiment of the present invention; and

FIGS. 16A and 16B are waveform diagrams of an operation of the thirdembodiment of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

In order to facilitate understanding of the present invention, adescription will first be given of related art of the present invention.

FIG. 1 is a block diagram of an SDRAM device. The SDRAM device includesa chip main body 1 on which a plurality of memory cell areas 2 through 5are formed. A block depicted by a two-dot chained line is an enlargementof the memory cell area 2 and part of a peripheral circuit of the memorycell area 2. The memory cell area 2 includes a memory cell array 6,which includes memory cells 7-10, word lines WL0 and WL1 for selectingmemory cells 7-10, and pair of bit lines BL0 and /BL0, and BL1 and /BL1.

FIG. 2 is a circuit diagram of the memory cell 7. The memory cell 7includes a cell capacitor 12 and a cell transistor 13. The cellcapacitor 12 functions to store data. The cell transistor 13 is turnedON/OFF by controlling the word line WL0 so that the charging anddischarging of the cell capacitor 12 can be controlled. A cell platevoltage VCP is applied to one end of the cell capacitor 12. The othermemory cells 8-10 are configured in the same manner as the memory cell7.

Turning now to FIG. 1, the SDRAM device includes a row 15 of senseamplifiers (S/A), each of which amplifies the difference between thepotentials of the corresponding pair of bit lines. A sense amplifier 16is provided to a pair of bit lines BL0 and /BL0, and a sense amplifier17 is provided to a pair of bit lines BL1 and /BL1.

FIG. 3 is a circuit diagram of the sense amplifier 16, which includespMOS (p-channel MOS) transistors 19 and 20, and nMOS (n-channel MOS)transistors, all of which transistors perform the amplifying operationof the sense amplifier. The pMOS transistors 19 and 20 perform thepull-up operation, and the nMOS transistors 21 and 22 perform thepull-down operation. Further, the sense amplifier 16 includes a pMOStransistor 23 and an nMOS transistor 24. The pMOS transistor 23 isturned ON and OFF in response to a sense amplifier activating signal/SAE. The nMOS transistor 24 is turned ON and OFF in response to a senseamplifier activating signal SAE. The pMOS transistor 23 is connected toa VCC power supply line VCC, and the nMOS transistor 24 is connected toa VSS ground line VSS.

Turning to FIG. 1 again, the sense amplifier includes a row 26 of columngates (CG) for selecting the columns. A column gate 27 is provided tothe pair of bit lines BL and /BL0, and a column gate 28 is provided tothe pair of bit lines BL1 and /BL1.

FIG. 4 is a circuit diagram of the column gates 27 and 28 shown inFIG. 1. The column gate 27 includes nMOS transistors 30 and 31controlled by a column selecting signal CL0. The column gate 28 includesnMOS transistors 32 and 33 controlled by a column selecting signal CL1.The column gates 27 and 28 are connected to a pair of local data buslines LDB and /LDB (local data transfer lines), which are commonlyprovided to other column gates as shown in FIG. 1. As shown in FIG. 1,the local data bus lines LDB and /LDB are respectively connected toglobal data bus lines GDB and /GDB through a data bus switch 35. A databus switch signal DSL is applied to the data bus switch 35, whichincludes nMOS transistors 36 and 37. An nMOS transistor 39 controlled bya shortcircuiting (precharging) signal SH is provided between the globaldata bus lines GDB and /GDB, which are commonly provided to other pairsof local data bus lines. Hereinafter, the nMOS transistor 39 is referredto as a precharging transistor.

A sense buffer (S/B) 40, which is connected to the pair of global databus lines GDB and /GDB, senses the potential difference therebetween andoutputs read data DO. A write amplifier (W/A) 41 drives the pair ofglobal data bus lines GDB and /GDB in response to write data DI. Theprecharging transistor 39 is disposed close to the input terminals ofthe sense buffer 40, in other words, the output terminals of the writeamplifier 41.

FIG. 5 is a circuit diagram of the sense buffer 40. The sense buffer 40includes a precharge circuit 43, which precharges the global data buslines GDB and /GDB to a precharge voltage VP lower than the power supplyvoltage VCC. The precharge circuit 43 includes nMOS transistors 44 and45 controlled by a precharge signal PC. When the circuit parts relatingto the column operate, the precharge signal PC is fixed to the powersupply voltage VCC.

The sense buffer 40 includes current-mirror amplifier circuits 46 and47. The current-mirror amplifier circuit 46 includes pMOS transistors 48and 49 functioning as input transistors, nMOS transistors 50 and 51connected in current-mirror formation, a pMOS transistor 52 enabling anddisabling the current-mirror circuit 46, and an nMOS transistor 53enabling and disabling the circuit 46. The current-mirror amplifiercircuit 47 includes pMOS transistors 54 and 55 functioning as inputtransistors, nMOS transistors 56 and 57 connected in current-mirrorformation, a pMOS transistor 58 enabling and disabling the circuit 47,and an nMOS transistor 59 enabling and disabling the circuit 47.

The sense buffer 40 includes NOR circuits 60 and 61, which form aflip-flop circuit, and an inverter 62 which inverts the output signal ofthe NOR circuit 60. A symbol RE denotes a read enable signal whichinstructs a read operation. A inverter 63 inverts the read enable signalRE. The read enable signal RE is high when the read operation isinstructed, and is low when the write operation is instructed.

The sense buffer 40 includes a NOR circuit 64, an inverter 65, and annMOS transistor 66. The NOR circuit 64 performs a NOR operation on theoutput signal of the NOR circuit 64 and the output signal of theinverter 63. The inverter 65 inverts the output signal of the NORcircuit 64. The nMOS transistor 66 is turned ON and OFF in response tothe output signal of the inverter 65. The pMOS transistor 58 and thenMOS transistor 59 are also turned ON and OFF in response to the outputsignal of the inverter 65.

The sense buffer 40 includes a NOR circuit 67, an inverter 68, and annMOS transistor 69. The NOR circuit 67 performs a NOR operation on theoutput signal of the NOR circuit 60 and the output signal of theinverter 63. The inverter 68 inverts the output signal of the NORcircuit 67. The nMOS transistor 69 is turned ON and OFF in response tothe output signal of the inverter 68. The pMOS transistor 52 and thenMOS transistor 53 are also turned ON and OFF in response to the outputsignal of the inverter 68.

When data on the global data bus lines GDB and /GDB is inverted at thetime of reading, one of the current-mirror amplifier circuits 46 and 47operates so that the read data DO is settled. Then, the current-mirroramplifier circuit which operates in the above process is disabled, whilethe other current-mirror amplifier circuit is enabled. In the above way,the sense buffer 40 is set to a standby mode ready to process a nextdata inversion occurring on the global data bus lines GDB and /GDB. Thatis, when the read data DO is alternately changed as indicated by"1"-→"0"-→"1"->"0", the current-mirror amplifier circuits 46 and 47 ofthe sense buffer 40 are alternately enabled one by one, so that a delayin accessing can be avoided.

FIG. 6 is a circuit diagram of the write amplifier 41, which includesinverters 71 and 72, which respectively inverts the write date DI.Further, the write amplifier 41 includes an inverter 73, which invertsthe output signal of the inverter 71. A symbol "WE" is a write enablesignal instructs the write operation. More particularly, the writeenable signal WE is high when the write operation is instructed, and islow when the read operation is instructed. The write amplifier 41includes an inverter 74, and transfer gates 75 and 76. The inverter 74inverts the write enable signal WE. The transfer gate 75 includes a PMOStransistor 75A and an nMOS transistor 75B. The transfer gate 76 includesa pMOS transistor 76A and an nMOS transistor 76B. When the write enablesignal WE is set to the high level, the transfer gates 75 and 76 areturned ON and enabled. When the write enable signal WE is set to the lowlevel, the transfer gates 75 and 76 are turned OFF and disabled.

In the read operation of the SDRAM device, each of the sense amplifiersincluding the amplifiers 16 and 17 shown in FIG. 1 amplifies thepotential difference between the corresponding pair of bit lines, thepotential difference resulting from discharging of the selected memorycell. Then, the pair of bit lines of the selected column is connected tothe pair of local data bus lines LDB and /LDB, and the selected pair oflocal data bus lines LDB and /LDB is connected to the pair of globaldata bus lines GDB and /GDB. In the above way, the data read from theselected memory cell is transferred, as complementary data signals, tothe sense buffer 40 through the sense amplifier, the local data buslines LDB and /LDB and the global data bus lines GDB and /GDB.

FIGS. 7A and 7B are waveform diagrams of an example of the readoperation, in which outputting of "0" from the sense amplifier 16 andoutputting of "1" from the sense amplifier are repeatedly performed.More particularly, FIG. 7A shows a voltage waveform of an external clockCLK supplied from an outside of the SDRAM device, voltage waveforms ofthe column selecting signals CL0 and CL1, and a voltage waveform of theshortcircuiting signal SH. FIG. 7B shows a voltage waveform of theexternal clock CLK, variations in the potentials of the bit lines BL0,/BL0, BL1 and /BL1, variations in the potentials of the local data buslines LDB and /LDB, and variations in the potentials of the global databus lines GDB and /GDB.

It can be seen from FIGS. 7A and 7B that high-speed read operation canbe realized in which the read operation is continuously performed anddata transfers of a small amplitude is carried out. When the readoperation is performed once, the precharging transistor 39 is turned ONto thereby shortcircuit the global data bus lines GDB and /GDB in orderto prevent a delay in the read operation in the next cycle. Hence, theglobal data bus lines GDB and /GDB as well as the selected local databus lines LDB and /LDB are precharged to the precharge voltage VP.

In the write operation, the write data DI is translated into thecomplementary data signals by means of the write amplifier 41, whichsignals are transferred to the sense amplifier of the selected columnvia the global data bus lines GDB and /GDB and the selected local databus lines LDB and /LDB. Then, the write data DI is finally written intothe selected cell via the corresponding pair of bit lines.

FIGS. 8A and 8B are waveform diagrams of an example of the writeoperation of the SDRAM device, and shows an operation in which, in acase where the sense amplifiers 16 and 17 respectively sense "0" and"1", (1) "1" is transferred to the sense amplifier 16, (2) "0" is thentransferred to the sense amplifier 17, (3) "1" is transferred to thesense amplifier 16, and (4) "0" is transferred to the sense amplifier17. More particularly, FIG. 8A shows a voltage waveform of the externalclock CLK, voltage waveforms of the column selecting signals CL0 andCL1, and a voltage waveform of the shortcircuiting signal SH. FIG. 8Bshows a voltage waveform of the external clock CLK, variations in thepotentials of the global data bus lines GDB and /GDB, variations in thevoltages of the local data bus lines LDB and /LDB, and variations in thevoltages of the bit lines BL0, /BL0, BL1 and /BL1.

The greater the potential difference between the complementary datasignals to be output to the global data bus lines GDB and /GDB from thewrite amplifier 41, the higher the write operation can be performed.When the write operation is performed once, the precharging transistor39 is turned ON, as in the case of the read operation, in order to avoidthe write operation in the next cycle from being prevented. Hence, theglobal data bus lines GDB and /GDB are shortcircuited, so that theglobal data bus lines GDB and /GDB and the local data bus lines LDB and/LDB are precharged to the precharged voltage VP.

The following means may contribute to reducing the operation cycle andspeeding up of the operation of the above SDRAM device. That is, whentaking into account the driving capability of the sense amplifier, it isnecessary to completely precharge, at the time of reading data, thelocal data bus lines LDB and /LDB and the global data bus lines GDB and/GDB to the precharge voltage VP and then transfer data ensured by thesense amplifier to the local data buses LDB and /LDB.

In the SDRAM device, as shown in FIGS. 7A, 7B, 8A and 8B, the timing atwhich the global data bus lines GDB and /GDB are shortcircuited toprecharge them is made to coincide with the shortcircuiting period.Hence, it is necessary to determine the period of shortcircuiting theglobal data bus lines GDB and /GDB on the basis of the data read timing.However, if the period for shortcircuiting is determined in the aboveway, when writing data, the global data bus lines GDB and /GDB areshortcircuited before the complementary data signals output to theglobal data bus lines GDB and /GDB from the write amplifier 41 have asufficient potential difference. This prevents speeding up of the readand write operations.

In the read operation of the above SDRAM device, data is transferred viathe selected sense amplifier, the selected local data bus lines LDB and/LDB, the global data bus lines GDB and /GDB, and the sense buffer 40 inthis order. In the write operation, data is transferred via the writeamplifier 41, the global data bus lines GDB and /GDB, the selected localdata bus lines LDB and /LDB and the selected sense amplifier in thisorder.

The precharging transistor 39 is disposed so as to shortcircuit theglobal data bus lines GDB and /GDB at a position close to the inputterminals of the sense buffer 40, that is, the output terminals of thewrite amplifier 41. That is, the precharging transistor 39 is located ata position far from the sense amplifier which is a driver fortransferring data in the read operation, and is located at a positionclose to the write amplifier which is a driver for transferring data inthe write operation.

The inventors took into consideration the above and found the followingfact through the research and experiments. When the operation cycle ismade short, the read operation can be performed at a higher speed bysufficiently performing the shortcircuiting operation on the global databus lines GDB and /GDB and then performing the data transfer operation.On the other hand, the write operation can be performed at a higherspeed by releasing the global data bus lines GDB and /GDB from theshortcircuited state before these lines are sufficiently shortcircuitedand then inverting data on the global data bus lines GDB and /GDB andthe selected local data bus lines LDB and /LDB due to the drivingcapability of the write amplifier 41 itself.

The present invention is based on the above fact found by the inventors.More particularly, the present invention is directed to a method andcircuit for shortcircuiting global data transfer lines of asemiconductor memory device in which complementary data signals aretransmitted over the transfer lines in order to write data in a memorycell array or read data therefrom. Further, the present invention isdirected to a semiconductor memory device having such a circuit.

A description will be given of embodiments of the present inventionwhich are SDRAM devices including a circuit for shortcircuiting datatransfer lines.

FIG. 9 is a block diagram of a first embodiment of the presentinvention. In FIG. 9, parts that are the same as those previouslydescribed are given the same reference numbers. The SDRAM device shownin FIG. 9 has a chip main body 80 having memory cell areas 81-84. Ablock depicted by a two-dot chained line is an enlarged portion of thememory cell area 81 and part of a peripheral circuit of the area 81.

The memory cell areas 81-84 have the same circuit configuration as thememory cell areas 2-5 shown in FIG. 1. An essential feature of the firstembodiment of the present invention is to have a control circuit 85.

FIG. 10 is a block diagram of a structure of the control circuit 85. Awrite/read indication signal W/R and a timing signal IN are applied tothe control circuit 85. The write/read indication signal W/R indicateswhether the write operation or the read operation is now in progress.The timing signal IN is synchronized with the external clock signal CLKsupplied from the outside of the SDRAM device. The control circuit 85includes inverters 87 and 88 connected in series. The control circuit 85includes a write enable controller 89, a read enable controller 95, awrite-time shortcircuiting controller 100, a read-time shortcircuitingcontroller 102, a shortcircuiting controller 106, and a columncontroller 111.

The write enabling controller 89 outputs the write enable signal WE tocontrol the enabling/disabling of the write amplifier 41. The controller89 includes inverters 90, 91, 93 and 94, and a NOR circuit 92. Theinverter 90 inverts the write/read indication signal W/R. The inverter91 inverts the output signal of the inverter 88. The NOR circuit 92performs a NOR operation on the output signals of the inverters 90 and91. The inverter 93 inverts the output signal of the NOR circuit 92. Theinverter 94 inverts the output signal of the inverter 93, and outputsthe write enable signal WE. The inverters 93 and 94 function as a delaycircuit.

The read enabling controller 95 outputs the read enable signal RE tocontrol the enabling/disabling of the sense buffer 40. The controller 95includes inverters 96, 98 and 99 and a NOR circuit 97. The inverter 96inverts the output signal of the inverter 88. The NOR circuit 97performs a NOR operation on the write/read indication signal W/R and theoutput signal of the NOR circuit 96. The inverter 98 inverts the outputsignal of the NOR circuit 97. The inverter 99 inverts the output signalof the inverter 98 to thereby generate the read enable signal RE. Theinverters 98 and 99 function as a delay circuit.

The write-time shortcircuiting controller 100 controls the timing atwhich the global data bus lines GDB and /GDB are shortcircuited at thetime of writing data. The controller 100 includes a NAND circuit, whichperforms a NAND operation on the write/read indication signal W/R andthe output signal of the inverter 88.

The read-time shortcircuiting controller 102 controls the timing atwhich the global data bus lines GDB and /GDB are shortcircuited at thetime of reading data. The controller 102 includes inverters 103 and 104,and a NAND circuit 105. The inverter 103 inverts the output signal ofthe inverter 88. The inverter 104 inverts the output signal of theinverter 103. The NAND circuit 105 performs a NAND operation on theoutput signal of the inverter 88 and the output signal of the inverter104. The inverters 103 and 104 function as a delay circuit.

The shortcircuiting controller 106 outputs the shortcircuiting signal SHto control the ON/OFF of the precharge transistor 39. The controller 106includes a NAND circuit 107 and inverters 108-110. The NAND circuit 107performs a NAND operation on an output signal S100 of the write-timeshortcircuiting controller 100 and an output signal S102 of theread-time shortcircuiting controller 012. The inverter 108 inverts theoutput signal of the NAND circuit 107. The inverter 109 inverts theoutput signal of the inverter 108. The inverter 110 inverts the outputsignal of the inverter 109 to thereby generate the shortcircuitingsignal SH. The inverters 108, 109 and 110 form an inverted delaycircuit.

The column controller 111 outputs the column control signal CL tocontrol the timing at which one column is selected. The controller 111includes inverters 112, 113, 116 and 117, and NAND circuits 114 and 115.The inverter 112 inverts the output signal of the inverter 88. Theinverter 113 inverts the output signal of the inverter 112. The NANDcircuit 114 functions to inverts the output signal of the inverter 113.The NAND circuit 115 functions to invert the output signal of the NANDcircuit 114. The inverter 116 inverts the output of the NAND circuit115. The inverter 117 inverts the output signal of the inverter 117 andoutput the column control signal CL.

FIGS. 11A and 11B are waveform diagrams of the operation of the firstembodiment of the present invention. More particularly, FIG. 11A shows aread operation, and FIG. 11B shows a write operation.

In the read operation, the write/read indication signal W/R is set tothe low level. In this case, when the timing signal IN is low, the writeenabling controller 89 operates as follows. The output signal of theinverter 90 is high, and the output signal of the inverter 91 is high.The output signal of the NOR circuit 92 is low, and the output signal ofthe inverter 93 is high. Hence, the write enable signal WE is low, andthe write amplifier 41 is in the disabled (inactive) state. In the readenabling controller 95, the output signal of the inverter 96 is high,and the output signal of the NOR circuit 97 is low. The output signal ofthe inverter 98 is high and thus the read enable signal RE are low.Hence, the sense buffer 40 is in the disabled state.

The output signal S100 of the write-time shortcircuiting controller 100becomes high. In the read-time shortcircuiting controller 102, theoutput signal of the inverter 103 is high and the output signal of theinverter 104 is low. Hence, the output signal S102 of the read-timeshortcircuiting controller 102 is high. Hence, in the shortcircuitingcontroller 106, the output signal of the NAND circuit 107 is low, andthe output signal of the inverter 108 is high. Further, the outputsignal of the inverter 109 is low. Thus, the shortcircuiting signal SHis high and the precharging transistor 39 is turned ON and the globaldata bus lines GDB and /GDB are set to the shortcircuited state.

In the column controller 111, the output signal of the inverter 112 ishigh, and the output signal of the inverter 113 is low. The outputsignal of the NAND circuit 114 is high, and the output signal of theNAND circuit 115 is low. The output signal of the inverter 116 is high,and thus the column control signal CL is low. Hence, the column is inthe non-selected state.

If the timing signal IN becomes high from the above non-selected state,the write enabling controller 89 operates as follows. The output signalof the inverter 91 is low, while the output signal of the inverter 90 ishigh, and the output signal of the NOR circuit 92 is low. Further, theoutput signal of the inverter 93 is high, and hence the write enablesignal WL is maintained at the low level. As a result, the disabledstate of o the write amplifier 41 is maintained.

In the read enabling controller 95, the output signal of the inverter 96is low, and the output signal of the NOR circuit 97 is high. The outputsignal of the inverter 98 is low, and the read enable signal RE is high.Hence, the sense buffer 40 is switched to the enabled state.

The output signal S100 of the write-time shortcircuiting controller 100is maintained at the high level. In the read-time shortcircuitingcontroller 102, the output signal of the inverter 103 becomes low andthe output signal of the inverter 104 becomes high. Hence, the outputsignal S102 of the read-time shortcircuiting controller 102 becomes low.Hence, in the shortcircuiting controller 106, output signal of the NANDcircuit 107 is high, and the output level of the inverter 108 is low.The output of the inverter 109 is high, and shortcircuiting signal SH isswitched to the low level. Hence, the precharging transistor 39 isturned OFF, and the global data bus lines GDB and /GDB are released fromthe shortcircuited state.

In the column controller 111, the output signal of the inverter 112 islow, and the output signal of the inverter 113 is high. The outputsignal of the NAND circuit 114 is low, and the output signal of the NANDcircuit 115 is high. The output signal of the inverter 116 is low, andthe column control signal CL is high. Hence, the column is selected.

The timing at which the shortcircuiting signal SH falls to the otherlevels is determined by the total of the delay times of the read-timeshortcircuiting controller 102 and the shortcircuiting controller 106.The timing at which the level of the column control signal CL isdetermined by the delay time of the column controller 111. The total ofthe delay times of the read-time shortcircuiting controller 102 and theshortcircuiting controller 106 is approximately equal to the delay timeof the column controller 111. Hence, the timing at which the level ofthe shortcircuiting signal SH substantially coincides with the timing atwhich the column control signal CL rises from the current level to theother level.

In the first embodiment of the present invention, the total of the delaytimes of the read-time shortcircuiting controller 102 and theshortcircuiting controller 106 is determined so that the releasing ofthe global data bus lines GDB and /GDB from the shortcircuited state iscarried out after the global data bus lines GDB and /GDB and theselected local data bus lines LDB and /LDB are precharged to theprecharged voltage VP. Thereafter, when the timing signal IN switches tothe low level, the output signal of only the inverter 91 is inverted tothe high level in the write enabling controller 89. That is, the outputsignals of the inverters 90 and 93 are maintained at the high level, andthe output signal of the NOR circuit 92 and the write enable signal WEare maintained at the low level. Hence, the write amplifier 41 ismaintained in the disabled state.

On the other hand, in the read activating controller 95, the outputsignal of the inverter 96 is high, and the output signal of the NORcircuit 97 is low. The output signal of the inverter 98 is high, and theread enable signal RE is low. Hence, the sense buffer 40 is switched tothe disabled state.

The output signal S100 of the write-time shortcircuiting controller 100is maintained at the high level, while the output signal S102 of theread-time shortcircuit controller 102 is switched to the high level.Hence, the shortcircuiting controller 106 operates as follows. Theoutput signal of the NAND circuit 107 is low, and the output signal ofthe inverter 108 is high. The output signal of the inverter 109 is low,and the shortcircuiting signal SH is high. Hence, the shortcircuitingtransistor 39 is turned ON and the global data bus lines GDB and /GDBare thus shortcircuited and precharged.

In the column controller 111, the output signal of the inverter 112 ishigh, and the output signal of the inverter 113 is low. The outputsignal of the NAND circuit 1143 is high, and the output signal of theNAND circuit 115 is low. The output signal of the inverter 116 is high,and the column control signal CL is low. Hence, the selection of thecolumn is terminated. The timing at which the level of theshortcircuiting signal SH increases substantially coincides with thetiming at which the level of the column control signal CL decreases.

A description will now be given of the write operation of the firstembodiment of the present invention.

In the write operation, the write/read indication signal W/R is switchedto the high level.

In this case, when the timing signal IN is low, the write enablingcontroller 89 operates as follows. The output signal of the inverter 90is low, and the output signal of the inverter 91 is high. The outputsignal of the NOR circuit 92 is low, and the output signal of theinverter 93 is high. Thus, the write enable signal WE is switched to thelow level, and the write amplifier 41 is set to the disabled state.

In the read enabling controller 95, the output signal of the inverter 96is low, and the output signal of the NOR circuit 97 is low. The outputsignal of the inverter 98 is high, and the read enable signal RE is low.Hence, the sense buffer 40 is set to the disabled state.

The output signal S100 of the write-time shortcircuit controller 100 isswitched to the high level. In the read-time shortcircuiting controller102, the output signal of the inverter 103 is high, and the outputsignal of the inverter 104 is low. Hence, the output signal S102 of theread-time shortcircuiting controller 102 is switched to the high level.Hence, in the shortcircuiting controller 106, the output signal of theNAND circuit 107 is low, and the output signal of the inverter 108 ishigh. The output signal of the inverter 109 is low, and theshortcircuiting signal SH is high. Hence, the precharging transistor 39is turned ON, and the global data bus lines GDB and /GDB are thus set tothe shortcircuited state.

In the column controller 111, the output signal of the inverter 112 ishigh, and the output signal of the inverter 113 is low. The outputsignal of the NAND circuit 114 is high, and the output signal of theNAND circuit 115 is low. The output signal of the inverter 116 is high,and the column control signal CL is low. Hence, the column is switchedto the disabled state.

When the timing signal IN becomes high from the above disabled state,the write enabling controller 89 operates as follows. The output signalof the inverter 91 is low, and the output signal of the NOR circuit 92is high. The output signal of the inverter 93 is low, and the writeenable signal WE is high. Hence, the write amplifier 41 is set to theenabled state.

The read enabling controller 95 operates as follows. Although the outputsignal of the inverter 96 is low, the write/read indication signal W/Ris maintained at the high level. Hence, the output signal of the NORcircuit 97 is low, and the output signal of the inverter 98 is high.Thus, the read enable signal RE is maintained at the low level, and thedisabled state of the sense buffer 40 is continuously held.

The output signal S100 of the write-time shortcircuiting controller 100is switched to the low level. Hence, in the shortcircuiting controller106, the output signal of the NAND circuit 107 is high, and the outputsignal of the inverter 108 is low. The output signal of the inverter 109is high, and the shortcircuiting signal SH is low. Hence, theshortcircuiting transistor 39 is turned OFF, and the global data buslines GDB and /GDB are released from the shortcircuited state.

In the read-time shortcircuiting controller 102, the output signal ofthe inverter 103 is switched to the low level and the output signal ofthe inverter 104 is switched to the high level. Hence, the output signalS102 of the read-time shortcircuiting controller 102 is switched to thelow level.

In the column controller 111, the output signal of the inverter 112 islow, and the output signal of the inverter 113 is high. The outputsignal of the NAND circuit 114 is low, and the output signal of the NANDcircuit 115 is high. The output signal of the inverter 116 is low, andthe column control signal CL is high. Hence, the column is selected.

The timing at which the shortcircuiting signal SH falls to the otherlevel is determined by the total of the delay times of the write-timeshortcircuiting controller 100 and the shortcircuiting controller 106.The timing at which the column control signal CL falls to the otherlevel is determined by the delay time of the column controller 111. Inthis case, the total of the delay times of the write-timeshortcircuiting controller 100 and the shortcircuiting controller 106 isshorter than the delay time of the column controller 111. Hence, thetiming at which the shortcircuiting signal SH falls leads to the timingat which the column control signal CL rises from the current level tothe other level.

In the first embodiment of the present invention, the total of the delaytimes of the write-time shortcircuiting controller 100 and theshortcircuiting controller 106 is determined so that the timing at whichthe shortcircuiting signal SH falls to the other level occurs before theglobal data bus liens GDB and /GDB and the selected local data bus linesLDB and /LDB are completely precharged to the precharge voltage VP.Further, the delay time of the write enabling controller 89 isdetermined so that the write operation is started at the same time asthe shortcircuiting transistor 39 is turned OFF.

Even in the above operation, it is possible to have a large drivingcapability of the write amplifier 41 and is possible for the writeamplifier 41 to invert the data on the global data bus lines GDB and/GDB and the selected local data bus lines LDB and /LDB.

Thereafter, when the timing signal IN becomes low, the write enablingcontroller 89 operates as follows. The output signal of the inverter 91is high, and the output signal of the NOR circuit 92 is low. The outputsignal of the inverter 93 is high, and the write enable signal WE is lowand therefore the write amplifier 41 is switched to the disabled state.

In the read enabling controller 95, the output signal of only theinverter 96 is inverted. That is, the output signal of the inverter 98is maintained at the high level, while the output signal of the NORcircuit 97 and the read enable signal RE are maintained at the lowlevel. Thus, the sense buffer 40 is maintained in the disabled state.

Further, the output signal S100 of the write-time shortcircuitingcontroller 100 is switched to the high level, and the output signal S102of the read-time shortcircuiting controller 102 is switched to the highlevel. Hence, in the shortcircuiting controller 106, the output signalof the NAND circuit 107 is low, and the output signal of the inverter108 is high. The output signal of the inverter 109 is low, and theshortcircuiting signal SH is high. Hence, the shortcircuiting transistor39 is turned ON, and the global data bus lines GDB and /GDB are switchedto the shortcircuited state and are thus precharged.

In the column controller 111, the output signal of the inverter 112 ishigh, and the output signal of the inverter 113 is low. The outputsignal of the NAND circuit 114 is high, and the output signal of theNAND circuit 115 is low. The output signal of the inverter 116 is high,and the column control signal CL is low. Hence, the selection of thecolumn is terminated. The timing at which the shortcircuiting signal SHrises to the other level substantially coincides with the timing atwhich the column control signal CL falls to the other level.

FIGS. 12A through 12E are waveform diagrams of a simulation of anexample of the operation of the first embodiment of the presentinvention. In the write operation, the sense amplifier 16 is made tosense data "0" and the sense amplifier 17 is made to sense data "1".Thereafter, data "1" is written into the sense amplifier 16, andsubsequently reading of "0" from the sense amplifier 17 and reading of"1" from the sense amplifier 16 are alternately carried out.

FIG. 12A shows a voltage waveform of the external clock CLK, and FIG.12B shows a voltage waveform of the write/read indication signal W/R.FIG. 12C shows a voltage waveform of the external clock CLK, variationsin the potentials of the bit lines BL0, /BL0, BL1 and /BL1, variationsin the potentials of the local data bus lines LDB and /LDB, andvariations in the potentials of the global data bus lines GDB and /GDB.FIG. 12D shows a voltage waveform of the external clock CLK, a voltagewaveform of the shortcircuiting signal SH, voltage waveforms of thecolumn selecting signals CL0 and CL1, and a voltage waveform of the readenable signal RE. FIG. 12E shows a voltage waveform of the externalclock CLK, a voltage waveform of the shortcircuiting signal SH, voltagewaveforms of the column selecting signals CL0 and CL1, a voltagewaveform of the write enable signal WE.

It can be seen from the operation cycles shown in FIGS. 12A through 12Ethat the global data bus lines GDB and /GDB are released from theshortcircuited state in the write operation in advance of releasingthese bus lines from the shortcircuited state in the read operation.This is one of the essential features of the first embodiment of thepresent invention.

Hence, it is possible to avoid the following problem and to reduce theoperation cycle and speed up the read and write operations. That is,even in the case where in the read operation, the selected local databus lines LDB and /LDB and the global data bus lines GDB and /GDB arecompletely precharged to the precharge voltage VP and thereafter datacaptured by the sense amplifier is transferred to the local data buslines, it is possible to avoid a situation in which the global data buslines GDB and /GDB are shortcircuited in the write operation before thecomplementary signals output to the global data bus lines GDB and /GDBfrom the write amplifier 41 have a sufficient potential difference.

The much faster write operation can be carried out by the writeamplifier 41 equipped with a driving capability of precharging theglobal data bus lines GDB and /GDB to the precharge voltage VP inadvance of precharging by the shortcircuiting transistor 39 and theprecharging circuit 43 which are the original precharging means.

A description will now be given, with reference FIGS. 13, 14A and 14B,of a second embodiment of the present invention, which is intended to beequipped with a control circuit shown in FIG. 13, which should besubstituted for the control circuit 85 shown in FIG. 10. The other partsof the second embodiment of the present invention are the same as thoseof the first embodiment thereof.

The control circuit shown in FIG. 13 is equipped with a read-time columncontroller 120, a write-time column controller 121 and a columncontroller 122, which are substituted for the column controller 111shown in FIG. 10. The other parts of the control circuit shown in FIG.13 are the same as those of the control circuit shown in FIG. 10.

The read-time column controller 120 controls the timing at which thecolumn control signal CL rises to the other level in the read operation,and is made up of inverters 123 and 124 and NAND circuits 125 and 126.The inverter 123 inverts the output signal of the inverter 88. Theinverter 124 inverts the output signal of the inverter 123. The NANDcircuit 125 functions as an inverter which inverts the output signal ofthe inverter 124. The NAND circuit 126 functions as an inverter whichinverts the output signal of the NAND circuit 125.

The write-time column controller 121 controls the timing at which thecolumn signal rises to the other level in the read operation, and itmade up of NAND circuits 127-129 and inverters 130 and 131. The NANDcircuit 127 performs a NAND operation on the output signals of thewrite/read indication signal W/R and the inverter 123. The NAND circuit128 functions as an inverter which inverts the output signal of the NANDcircuit 127. The NAND circuit 129 functions as an inverter which invertsthe output signal of the NAND circuit 128. The inverter 130 inverts theoutput signal of the NAND circuit 129. The inverter 131 inverts theoutput signal of the inverter 130.

The column controller 122 outputs the column selecting signal CL tothereby control the column selecting operation, and is made up of a NANDcircuit 132 and an inverter 133. The NAND circuit 132 performs a NANDoperation on an output signal S120 of the read-time column controller120 and an output signal of the write-time column controller 121. Theinverter 133 inverts the output signal of the NAND circuit 132 tothereby output the column control signal CL.

FIGS. 14A and 14B are waveform diagrams of an operation of the secondembodiment of the present invention. More particularly, FIG. 14A shows aread operation, and FIG. 14B shows a write operation. The write enablingcontroller 89, the read enabling controller 95, the write-timeshortcircuiting controller 100, the read-time shortcircuiting controller102 and the shortcircuiting controller 106 of the second embodiment ofthe present invention operate in the same manner as those of the firstembodiment of the present invention.

In the read operation, the write/read indication signal W/R is set tothe low level. In this case, when the timing signal IN is low, theread-time column controller 120 operates as follows. The output signalof the inverter 123 is high, and the output signal of the inverter 124is low. The output signal of the NAND circuit 125 is high, and theoutput signal S120 of the read-time column controller 120 is low.

In the write-time column controller 121, the output signal of the NANDcircuit 127 is high, and the output signal of the NAND circuit 128 islow. The output signal of the NAND circuit 129 is high, and the outputsignal of the inverter 130 is low. Thus, the output signal S121 of thewrite-time column controller 121 is high. Hence, the output signal ofthe NAND circuit 132 is high and the column control signal CL is low.

When the timing signal switches to the high level from the above state,the read-time column controller 120 operates as follows. The outputsignal of the inverter 123 is low, and the output signal of the inverter124 is high. The output signal of the NAND circuit is low, and theoutput signal S120 of the read-time column controller 120 is high.

In the write-time column controller 121, the output signal of the NANDcircuit 127 is high, and the output signal of the NAND circuit 128 islow. The output signal of the NAND circuit 129 is high, and the outputsignal of the inverter 130 is low. Hence, the output signal S121 of thewrite-time column controller 121 is maintained at the high level. Hence,the output signal of the NAND circuit 132 of the column controller 122is switched to the low level and the column control signal CL isswitched to the high level.

The timing at which the column control signal CL rises to the otherlevel is determined by the total of the delay times of the read-timecolumn controller 120 and the column controller 122. The total of theread-time column controller 120 and the column controller 122 isapproximately equal to the total of the delay times of the read-timeshortcircuiting controller 102 and the shortcircuiting controller 106.Hence, the timing at which the column controller signal CL rises to theother level substantially coincides with the timing obtained in thefirst embodiment of the present invention.

Thereafter, when the timing signal IN becomes low, the read-time columncontroller 120 operates as follows. The output signal of the inverter123 is high, and the output signal of the inverter 124 is low. Theoutput signal of the NAND circuit 125 is high, and the output signalS120 of the read-time column controller 120 is low. Hence, the outputsignal of the NAND circuit 132 of the column controller 122 is high, andthe column control signal CL is low. The timing at which the columncontrol signal CL falls is almost the same as that of the firstembodiment of the present invention.

In the write-time column controller 121, the output signal of the NANDcircuit 127 is high, and the output signal of the NAND circuit 128 islow. The output signal of the NAND circuit 129 is high, and the outputsignal of the inverter 130 is low. Thus, the output signal S121 of thewrite-time column controller 121 is maintained at the high level.

In the write operation, the write/read indication signal W/R is set tothe high level. In this case, when the timing signal IN is at the lowlevel, the read-time column controller 120 operates as follows. Theoutput signal of the inverter 123 is high, and the output signal of theinverter 124 is low. The output signal of the NAND circuit 125 is high,and the output signal S120 of the read-time column controller 120 islow.

In the write-time column controller 121, the output signal of the NANDcircuit 127 is low, and the output signal of the NAND circuit 128 ishigh. The output signal of the NAND circuit 129 is low, and the outputsignal of the inverter 130 is high. Thus, the output signal S121 of thewrite-time column controller 121 is low. Hence, in the column controller122, the output signal of the NAND circuit 132 is low, and the columncontrol signal CL is low.

When the timing signal IN becomes high from the above state, theread-time column controller 120 operates as follows. The output signalof the inverter 123 is low and the output signal of the inverter 124 ishigh. The output signal of the NAND circuit 125 is low and the outputsignal S120 of the read-time column controller 120 is high.

In the write-time controller 121, the output signal of the NAND circuit127 is high and the output signal of the NAND circuit 128 is low. Theoutput signal of the NAND circuit 129 is high, and the output signal ofthe inverter 130 is low. Hence, the output signal S121 of the write-timecolumn controller 121 is high. Hence, in the column controller 122, theoutput signal of the NAND circuit 132 is low and the column controlsignal CL is high.

It will be noted that the output signal S121 of the write-time columncontroller 121 is switched to the high level with a delay equal to thetotal of the delay time of one NAND circuit and the delay time of oneinverter after the output signal S120 of the read-time column controller120 is switched to the high level. Hence, the timing at which the columncontrol signal CL is switched to the low level is delayed as compared tothe timing of the first embodiment of the present invention. The brokenline Z shown in FIG. 14B indicates the column control signal CL used inthe first embodiment of the present invention.

Thereafter, when the timing signal IN becomes low, the read-time columncontroller 120 operates as follows. The output signal of the inverter123 is high and the output signal of the inverter 124 is low. The outputsignal of the NAND circuit 125 is high, and the output signal S120 ofthe read-time column controller 120 is low. Hence, in the columncontroller 122, the output signal of the NAND circuit 132 is high, andthe column control signal CL is low.

In the write-time column controller 121, the output signal of the NANDcircuit is low and the output signal of the NAND circuit 128 is high.The output signal of the NAND circuit 129 is low and the output signalof the inverter 130 is high. Hence, the output signal S121 of thewrite-time column controller 121 is low. The timing at which the signalS121 become low lags behind the timing at which the output signal S120of the read-time column controller 120 becomes low. Hence, the timing atwhich the column control signal CL becomes low substantially coincideswith that of the first embodiment of the present invention.

In the first embodiment of the present invention, if the chip size islarge and the data transfer lines are long, the column gate may beselected before the complementary data signals output to the global databus lines GDB and /GDB from the write amplifier 41 reach the selectedcolumn gate. In this case, if the data captured by the sense amplifierof the selected column has the inverted relationship with the data to bewritten into the selected memory cell, two pairs of complementarysignals having the inverted relationship collide on the selected pair oflocal data bus lines. This collision may cause a delay in signaltransfer.

With the above in mind, in the second embodiment of the presentinvention, the timing at which the column control signal CL rises isdesigned to lag behind the corresponding timing of the first embodimentof the present invention. Hence, it is possible to settle the potentialsof the selected pair of local data bus lines and thereafter write datainto the sense amplifier of the selected column.

Hence, it is possible to avoid the following problems and to reduce theoperation cycle and speed up the read and write operations. That is,even in the case where the read operation, the selected local data buslines LDB and /LDB and the global data bus lines GDB and /GDB arecompletely precharged to the precharge voltage VP and thereafter datacaptured by the sense amplifier is transferred to the local data buslines, it is possible to avoid a situation in which the global data buslines GDB and /GDB are shortcircuited in the write operation before thecomplementary signals output to the global data bus lines GDB and /GDBfrom the write amplifier 41 have a sufficient potential difference.Further, it is possible to avoid a delay in data transfer due to acollision of the complementary data signals output to the global databus lines GDB and /GDB from the write amplifier 41 and the complementarydata signals output from the sense amplifier and to thereby speed up theread and write operations.

A description will now be given, with reference to FIGS. 15, 16A and16B, of a third embodiment of the present invention, which is equippedwith a control circuit shown in FIG. 15 instead of the control circuit85 shown in FIG. 10. The other parts of the third embodiment of thepresent invention are the same as those of the first embodiment of thepresent invention.

The control circuit shown in FIG. 15 has a write controller 135, and isequipped with a read-time column controller 136 having a differentconfiguration from that of the read-time column controller 120 shown inFIG. 13. The other parts of the control circuit shown in FIG. 15 are thesame as those of the control circuit shown in FIG. 13.

A case will now be assumed in which the timing at which the columncontrol signal CL falls to the other level in the write operation isdelayed to ensure a sufficient write time. In this case, if the controlcircuit shown in FIG. 13 is used, it is necessary to delay the timing atwhich the output signal S120 of the read-time column controller 120falls. In this case, a problem may be caused in which the column controlsignal CL rises to the other level from the current level. The thirdembodiment of the present invention is directed to eliminating the aboveproblem.

The write controller 135 includes inverters 137 and 138 and a NANDcircuit 139. The inverter 137 inverts a word/read indication signal W/R.The inverter 138 inverts the output signal of the inverter 137. The NANDcircuit 139 performs a NAND operation on the output signal of theinverter 138 and the word/read indication signal W/R. A delay circuit isformed by the inverters 137 and 138.

When the operation mode of the memory device is switched from the readmode to the write mode, the write controller 135 outputs the invertedversion of the word/read indication signal W/R with a delay equal to thesum of the delay times of the inverters 137 and 138 and the NAND circuit139. The output signal of the write controller 135 is supplied to theread-time column controller 136. When the operation mode is switchedfrom the write mode to the read mode, the write controller 135 suppliesthe read-time column controller 136 with the word/read indication signalW/R with the delay time of the NAND circuit 139.

The read-time column controller 136 has a NAND circuit 140, which issubstituted for the inverter of the read-time column controller 120shown in FIG. 13. The NAND circuit 140 performs a NAND operation on theoutput signal of the inverter 123 and the output signal of the writecontroller 135. The output signal of the NAND circuit 140 is supplied tothe NAND circuit 125. The other parts of the read-time column controller136 are the same as those of the read-time column controller 120. TheNAND circuits 125 and 126 form a delay circuit, and the NAND circuits128 and 129 and inverters 130 and 131 form another delay circuit.

FIGS. 16A and 16B are waveform diagrams of an operation of the thirdembodiment of the present invention. More particularly, FIG. 16A shows aread operation, and FIG. 16B shows a write operation. The write enablingcontroller 89, the read enabling controller 95, the write-timeshortcircuiting controller 100, the read-time shortcircuiting controller106 of the third embodiment of the present invention operate in the samemanner as those of the first embodiment of the present invention.

In the read operation, the write/read indication signal W/R is set tothe low level. In this case, the write controller 135 operates so thatthe output signals of the inverters 137 and 138 are high and low,respectively, and the output signal of the NAND circuit 139 is high. Inthis case, when the timing signal IN is low, the read-time columncontroller 136 operates as follows. The output signal of the inverter123 is high, and the output signal of the NAND circuit 140 is low. Theoutput signal of the NAND circuit 125 is high, and the output signalS136 of the read-time column controller 136 is low.

The write-time column controller 121 operates as follows. The outputsignal of the NAND circuit 127 is high, and the output signal of theNAND circuit 128 is low. The output signal of the NAND circuit 129 ishigh, and the output signal of the inverter 130 is low. Thus, the outputsignal S121 of the write-time column controller 121 is high. Hence, inthe column controller 122, the output signal of the NAND circuit 132 ishigh, and the column control signal CL is low.

When the timing signal IN switches to the high level from the abovestate, the read-time column controller 136 operates as follows. Theoutput signal of the inverter 123 is low, and the output signal of theNAND circuit 140 is high. The output signal of the NAND circuit 125 islow, and the output signal S136 of the read-time column controller 136is high. Hence, in the column controller 122, the output signal of theNAND circuit 132 is low, and the column control signal CL is high.

In the write-time column controller 121, the output signal of the NANDcircuit 127 is high, and the output signal of the NAND circuit 128 islow. The output signal of the NAND circuit 129 is high, and the outputsignal of the inverter 130 is low. Hence, the output signal S121 of thewrite-time column controller 121 is maintained at the high level.

The timing at which the column control signal CL is switched to the highlevel, is determined by the total of the delay times of the read-timecolumn controller 136 and the column controller 122. The total of thedelay times of the read-time column controller 136 and the columncontroller 122 is approximately equal to the total of the delay times ofthe read-time shortcircuiting controller 102 and the shortcircuitingcontroller 106. Hence, the timing at which the column control signal CLis switched to the high level substantially coincides with that of thefirst embodiment of the present invention.

Thereafter, if the timing signal IN becomes low, the read-time columncontroller 136 operates as follows. The output signal of the inverter123 is high, and the output signal of the NAND circuit 140 is low. Theoutput signal of the NAND circuit 125 is high, and the output signalS136 of the read-time column controller 136 is low.

Hence, in the column controller 122, the output signal of the NANDcircuit 132 is high, and the column control signal CL is low. The timingat which the column control signal CL is low substantially coincideswith that of the first embodiment of the present invention.

In the write operation, the write/read indication signal W/R is switchedto the high level. In this case, the write controller 135 operates sothat the output signal of the inverters 137 and 138 are low and high,respectively, and the output signal of the NAND circuit 139 is low.

When the timing signal IN is low, the read-time column controller 136operates as follows. The output signal of the inverter 123 is high andthe output signal of the NAND circuit 140 is high. The output signal ofthe NAND circuit 125 is low, and the output signal S136 of the read-timecolumn controller 136 is high. In the write-time column controller 121,the output signal of the NAND circuit 127 is low, and the output signalof the NAND circuit 128 is high. The output signal of the NAND circuit129 is low, and the output signal of the inverter 130 is high. Hence,the output signal S121 of the write-time column controller 121 is low.Hence, in the column controller 122, the output signal of the NANDcircuit 132 is high, and the column control signal CL is low.

When the timing signal IN switches to the high level from the abovestate, the read-time column controller 136 operates as follows. Althoughthe output signal of the inverter 123 is low, the output signal of theNAND circuit 140 is high, and the output signal of the NAND circuit 125is low. Hence, the output signal S136 of the read-time column controller136 is maintained at the high level. In the write-time column controller121, the output signal of the NAND circuit 127 is high, and the outputsignal of the NAND circuit 128 is low. The output signal of the NANDcircuit 129 is high, and the output signal of the inverter 130 is low.Hence, the output signal S121 of the write-time column controller 121 ishigh. Hence, in the column controller 122, the output signal of the NANDcircuit 132 is low, and the column control signal CL is high.

The timing at which the column control signal CL rises is determined bythe total of the delay times of the write-time column controller 121 andthe column controller 122. The total of the delay times of thewrite-time column controller 121 and the column controller 122 is longerthan the total of the delay times of the read-time column controller 136and the column controller 122, and is therefore much more delayed thanthat of the first embodiment of the present invention (but is equal tothe total delay time of the second embodiment of the present invention).A broken line Z shown in FIG. 16B indicates the column control signal CLused in the first embodiment of the present invention.

Thereafter, when the timing signal IN becomes low, the read-time columncontroller 136 operates as follows. Although the output signal of theinverter 123 is high, the output signals of the NAND circuits 140 and125 are respectively high and low. Hence, the output signal S136 of theread-time column controller 136 is maintained at the high level. In thewrite-time column controller 121, the output signal of the NAND circuit127 is low, and the output signal of the NAND circuit 128 is high. Theoutput signal of the NAND circuit 129 is low, and the output signal ofthe inverter 130 is high. Hence, the output signal S121 of thewrite-time column controller 121 is low. Hence, in the column controller122, the output signal of the NAND circuit 132 is high, and the columncontrol signal CL is low.

The timing at which the column control signal CL falls is determined bythe total of the write-time column controller 121 and the columncontroller 122 as in the case of the rising of the column control signalCL. Hence, the above falling timing is much more delayed than thetimings in the first and second embodiments of the present invention.Hence, the column control signal CL used in the write operation has awaveform which is just like a delayed version of the column controlsignal CL used in the read operation. Hence, it is possible to ensure asufficient write time.

In this case, there is no problem in which the column control signal CLrises and the corresponding column is selected when the operation modeis switched from the read mode to the write mode or vice versa. That is,in the case where the write/read indication signal W/R is switched tothe low level to enable the read mode, the write-time column controller121 operates as follows. The output signal of the NAND circuit 127 ishigh, and the output signal of the NAND circuit 128 is low. The outputsignal of the NAND circuit 129 is high, and the output signal of theinverter 130 is low. Further, the output signal of the inverter 131 ishigh.

In the write controller 135, the output signal of the inverters 137 and138 are respectively high and low, and the output signal of the NANDcircuit 139 is high. In the read-time column controller 136, the outputsignal of the inverter 123 is high, and the output signal of the NANDcircuit 140 is low. The output signal of the NAND circuit 125 is high,and the output signal of the NAND circuit 126 is low. In the columncontroller 122, the output signal o the NAND circuit 132 is high, andthe column control signal CL is low.

When the write/read indication signal W/R is switched to the high levelto enable the write mode, the write controller 135 operates as follows.The output signal of the inverter 137 is low, and the output signal ofthe inverter 138 is high. The output signal of the NAND circuit 139 islow. Hence, in the read-time column controller 136, the output signal ofthe NAND circuit 140 is high, and the output signal of the NAND circuit125 is low. The output signal of the NAND circuit 126 is high.

In the write-time column controller 121, the output signal of the NANDcircuit 127 is low, and the output signal of the NAND circuit 128 ishigh. The output signal of the NAND circuit 128 is low, and the outputsignal of the inverter 130 is high. The output signal of the inverter131 is low.

The timing at which the output signal S136 of the read-time columncontroller 136 is inverted to the high level is determined by the totalof the delay times of the inverters 137 and 138 and the NAND circuits139, 140, 125 and 126. The timing at which the output signal S121 of thewrite-time column controller 121 is inverted to the low level isdetermined by the total of the delay times of the NAND circuits 127-129and the inverters 130 and 131.

Hence, in this case, the timing at which the output signal S136 of theread-time column controller 136 is inverted to the high level leads tothe timing at which the output signal S121 of the write-time columncontroller 121 is inverted to the low level. In the column controller122, the output signal of the NAND circuit 132 is high, and the columncontrol signal CL is maintained at the low level.

When the timing signal IN becomes low in the case where the write/readindication signal W/R is set to the high level to enable the writeoperation, the write controller 135 operates as follows. The outputsignals of the inverters 137 and 138 are respectively low and high, andthe output signal of the NAND circuit 139 is low. In the read-timecolumn controller 136, the output signal of the inverter 123 is high,and the output signal of the NAND circuit 140 is high. The output signalof the NAND circuit 125 is low, and the output signal of the NANDcircuit 126 is high.

In the write-time column controller 121, the output signal of the NANDcircuit 127 is low, and the output signal of the NAND circuit 128 ishigh. The output signal of the NAND circuit 129 is low, and the outputsignals of the inverters 130 and 131 are high and low, respectively. Inthe column controller 122, the output signal of the NAND circuit 132 ishigh, and the column control signal CL is low.

When the write/read indication signal W/R is switched to the low levelto thereby enable the read mode, the write-time column controller 121operates as follows. The output signal of the NAND circuit 127 is high,and the output signal of the NAND circuit 128 is low. The output signalof the NAND circuit 129 is high, and the output signals of the inverters130 and 131 are low and high, respectively.

In the write controller 135, the output signal of the NAND circuit 139is high. Hence, in the read-time column controller 136, the outputsignal of the NAND circuit 140 is low, and the output signal of the NANDcircuit 125 is high. Further, the output signal of the NAND circuit 126is low.

The timing at which the output signal S121 of the write-time columncontroller 121 is inverted to the high level is determined by the totalof the delay times of the NAND circuits 127-129 and the inverters 130and 131. The timing at which the output signal S136 of the read-timecolumn controller 136 is switched to the low level is determined by thetotal of the delay times of the NAND circuits 139, 140, 125 and 126.

In the above case, the timing at which the output signal S121 of thewrite-time column controller 121 is inverted to the high level leads tothe timing at which the output signal S136 of the read-time columncontroller 136 is inverted to the low level. Thus, in the columncontroller 122, the output signal of the NAND circuit 132 is high andthe column control signal CL is maintained at the low level.

According to the third embodiment of the present invention, it ispossible to avoid the following problems and to reduce the operationcycle and speed up the read and write operations. That is, even in thecase where in the read operation, the selected local data bus lines LDBand /LDB and the global data bus lines GDB and /GDB are completelyprecharged to the precharge voltage VP and thereafter data captured bythe sense amplifier is transferred to the local data bus lines, it ispossible to avoid a situation in which the global data bus lines GDB and/GDB are shortcircuited in the write operation before the complementarysignals output to the global data bus lines GDB and /GDB from the writeamplifier 41 have a sufficient potential difference. Further, it ispossible to avoid a delay in data transfer due to a collision of thecomplementary data signals output to the global data bus lines GDB and/GDB from the write amplifier 41 and the complementary data signalsoutput from the sense amplifier and to thereby speed up the read andwrite operations. Furthermore, it is possible to lengthen the high-levelperiod of the column control signal CL to speed up the read and writeoperations.

In the above-mentioned first through third embodiments of the presentinvention, the shortcircuiting transistor 39 and the precharging circuit43, which operates when the column-system circuits operate, are providedas means for precharging the global data bus lines GDB and /GDB and theselected local data bus lines LDB and /LDB. However, it is possible toomit the precharging circuit 43.

It is possible to replace the precharging circuit 43 by anotherprecharging circuit which performs the precharging operation in responseto a signal synchronized with the shortcircuiting signal SH. Moreparticularly, the substitute precharging circuit operates during theperiod when the column-system circuits operate. That is, the substituteprecharging circuit supplies the precharge voltage VP to the global databus lines GDB and /GDB during the period when these bus lines are beingshortcircuited. The substitute precharging circuit do not supply theprecharge voltage VP to the global data bus lines GDB and /GDB duringthe period when these bus lines are not in the precharged state.

In the above-mentioned first through third embodiments of the presentinvention, a plurality of pairs of local data bus lines and a pair ofglobal data bus lines are used. However, the present invention includesa semiconductor memory device in which data buses are not divided intolocal and global data buses, but the shortcircuiting transistor 39, thesense buffer 40 and the write amplifier 41 are connected to the data busto which the sense amplifier is connected.

The present invention is not limited to the SDRAM devices but includeanother memory device such as an asynchronous-type DRAM device in whichthe read and write operations can continuously be carried out.

The present invention is not limited to the specifically disclosedembodiments and variations and modifications may be made withoutdeparting from the scope of the present invention.

What is claimed is:
 1. A method of controlling data transmission linesof a semiconductor memory .[.device.]. which has a first pair of datatransmission lines to which a sense amplifier and memory cells areconnected, and a second pair of data transmission lines to which a readcircuit and a write circuit are connected .[.at an end of the secondpair of the data transmission lines.]., .Iadd.and .Iaddend.which isconnected to the first pair of data transmission lines via a .[.columngate.]. .Iadd.switch.Iaddend., said method comprising:a) shortcircuitingthe second pair of data transmission lines for a first period .[.when aread operation is carried out.]. .Iadd.in a read mode.Iaddend.; and b)shortcircuiting the second pair of data transmission lines for a secondperiod .[.when a write operation is carried out.]. .Iadd.in a writemode.Iaddend., and second period being shorter than the first period. 2.A semiconductor .[.device.]. .Iadd.memory .Iaddend.comprising:memorycells; a sense amplifier; a first pair of data transmission lines towhich the sense amplifier and .Iadd.the .Iaddend.memory cells areconnected; a second pair of data transmission lines to which a readcircuit and a write circuit are connected .[.at an end of the secondpair of the data transmission lines.]., .Iadd.and .Iaddend.which isconnected to the first pair of data transmission lines via a .[.columngate.]. .Iadd.switch.Iaddend.; a shortcircuiting element which canshortcircuit the second pair of transmission a first control circuitwhich controls the shortcircuiting element so that the second pair ofdata transmission lines is shortcircuited for a first period .[.when aread operation is carried out.]. .Iadd.in a read mode.Iaddend., and thesecond pair of data transmission lines is shortcircuited for a secondperiod .[.when a write operation is carried out.]. .Iadd.in the writemode.Iaddend., said second period being shorter than the first period..[.
 3. The semiconductor memory device as claimed in claim 2, whereinthe second pair of data transmission lines comprises:a third pair ofdata transmission lines to which the first pair of data transmissionlines is connected; and a fourth pair of data transmission lines towhich the read circuit and the write circuit are connected, the fourthpair of data transmission lines being coupled to the third pair of datatransmission lines via a switch circuit..].
 4. The semiconductor memory.[.device.]. as claimed in claim 2, further comprising a prechargingcircuit which supplies a precharge voltage to the second pair of datatransmission lines.
 5. The semiconductor memory .[.device.]. as claimedin claim 4, wherein said precharging circuit supplies the prechargevoltage to the second pair of data transmission lines while the secondpair of data transmission lines is being shortcircuited, and does notsupply the precharge voltage thereto when the second pair of datatransmission lines is not shortcircuited.
 6. The semiconductor memory.[.device.]. as claimed in claim 2, .Iadd.further comprising:a columngate controlled by a first signal, and disposed between the first pairof data transmission lines and the sense amplifier, and .Iaddend.whereinthe first control circuit controls the shortcircuiting element so that atiming at which the second pair of data transmission lines .[.is.]..Iadd.initiates to be .Iaddend.shortcircuited substantially coincideswith .[.a.]. .Iadd.an inactivation timing of the .Iaddend.first signal.[.defining an operation timing.]. in the read and write.[.operations.]. .Iadd.modes.Iaddend., and a timing at which the secondpair of data transmission lines is released from a shortcircuited statein the write .[.operation.]. .Iadd.mode .Iaddend.is earlier.[., withrespect to.]. .Iadd.than an activation timing of .Iaddend.the firstsignal, .Iadd.and .Iaddend.than a timing at which the second pair ofdata transmission lines is released from the shortcircuited state in theread .[.operation.]. .Iadd.mode..Iaddend.
 7. The semiconductor memory.[.device.]. as claimed in claim 4, wherein the first control circuitcontrols the shortcircuiting element so that the second pair of datatransmission lines is released from a shortcircuited state in the read.[.operation.]. .Iadd.mode .Iaddend.after the second pair of datatransmission lines .[.is.]. .Iadd.completes to be .Iaddend.precharged tothe precharge voltage.
 8. The semiconductor memory .[.device.]. asclaimed in claim 4, wherein the first control circuit controls theshortcircuiting element so that the second pair of data transmissionlines is released from a shortcircuited state in the write.[.operation.]. .Iadd.mode .Iaddend.before the second pair of datatransmission lines .[.is.]. .Iadd.completes to be .Iaddend.precharged tothe precharge voltage.
 9. The semiconductor memory .[.device.]. asclaimed in claim 8, wherein said write circuit has a driving capabilityof setting the second pair of data transmission lines to the prechargevoltage .[.faster.]..Iadd., when the write circuit inverts complementarysignals on the second pair of data transmission lines larger.Iaddend.than .Iadd.driving capability of .Iaddend.the prechargingcircuit .[.precharges.]. .Iadd.precharging .Iaddend.the second pair ofdata transmission lines to the precharge voltage .[.when the writecircuit inverts complementary signal on the second pair of datatransmission lines.]..
 10. The semiconductor memory .[.device.]. asclaimed in claim 2, wherein said first control circuit comprises:asecond control circuit which controls timings at which the second pairof data transmission lines is .[.shortcircuited and.]. released from ashortcircuited state in the write .[.operation.]. .Iadd.mode.Iaddend.; athird control circuit which controls timings at which the second pair ofdata transmission lines is shortcircuited and released from theshortcircuited state in the read .[.operation.]. .Iadd.mode.Iaddend.;and a fourth control circuit which controls a timing at which theshortcircuiting element shortcircuits .Iadd.and releases from theshortcircuited state of .Iaddend.the second pair of data transmissionlines .[.on the basis of.]. .Iadd.in response to .Iaddend.output signalsof the second and third control circuits.
 11. The semiconductor memory.[.device.]. as claimed in claim 10, wherein:the second control circuitcomprises a first NAND circuit which .[.performs a NAND operation on.]..Iadd.receives .Iaddend.a .[.first.]. .Iadd.second .Iaddend.signaldefining an operation timing and a .[.second.]. .Iadd.third.Iaddend.signal indicating .[.whether an operation mode of thesemiconductor memory device is.]. the write .[.operation.]. .Iadd.mode.Iaddend.or the read .[.operation.]. .Iadd.mode.Iaddend.; the thirdcontrol circuit comprises a first delay circuit delaying the .[.first.]..Iadd.second .Iaddend.signal, and a second NAND circuit .[.performing aNAND operation.]. .Iadd.receiving .Iaddend.an output signal of the firstdelay circuit and the .[.first.]. .Iadd.second .Iaddend.signal; and thefourth control circuit comprises a third NAND circuit .[.performing aNAND operation on.]. .Iadd.receiving .Iaddend.an output signal of thesecond control circuit and an output signal of the third controlcircuit, and a first inverting delay circuit which inverts and delays anoutput signal of the third NAND circuit.
 12. The semiconductor memory.[.device.]. as claimed in claim 11, wherein the .[.first.]..Iadd.second .Iaddend.signal is a signal synchronized with an externalclock applied to the semiconductor memory .[.device.]..
 13. Thesemiconductor memory .[.device.]. as claimed in claim 2, furthercomprising a .[.second.]. .Iadd.fifth .Iaddend.control circuit which.[.controls enabling of.]. .Iadd.activates .Iaddend.the write circuitwhich outputs data to the second pair of data transmission lines atalmost the same time as the second pair of data transmission lines isreleased from a shortcircuited state.
 14. The semiconductor memory.[.device.]. as claimed in claim 13, wherein said .[.second.]..Iadd.fifth .Iaddend.control circuit controls the write circuit .[.onthe basis of.]. .Iadd.in response to .Iaddend.a .[.first.]. .Iadd.second.Iaddend.signal defining an operation timing and a .[.second.]..Iadd.third .Iaddend.signal indicating .[.whether an operation mode ofthe semiconductor memory device is.]. the write .[.operation.]..Iadd.mode .Iaddend.or the read .[.operation.]. .Iadd.mode.Iaddend.. 15.The semiconductor memory .[.device.]. as claimed in claim 14, whereinsaid .[.second.]. .Iadd.fifth .Iaddend.control circuit comprises:a firstinverting circuit which inverts the .[.first.]. .Iadd.second.Iaddend.signal; a second inverting circuit which inverts the.[.second.]. .Iadd.third .Iaddend.signal; a first NOR circuit which.[.performs a NOR operation on.]. .Iadd.receives .Iaddend.output signalsof the first and second inverting circuits; and a .[.first.]..Iadd.second .Iaddend.delay circuit which delays an output signal of thefirst NOR circuit.
 16. The semiconductor memory .[.device.]. as claimedin claim 2, further comprising a .[.second.]. .Iadd.sixth.Iaddend.control circuit which .[.controls enabling of.]..Iadd.activates .Iaddend.the .[.write.]. .Iadd.read .Iaddend.circuit.[.on the basis of.]. .Iadd.in response to .Iaddend.a .[.first.]..Iadd.second .Iaddend.signal defining an operation timing and a.[.second.]. .Iadd.third .Iaddend.signal indicating .[.whether anoperation mode of the semiconductor memory device is.]. the write.[.operation.]. .Iadd.mode .Iaddend.or the read .[.operation.]..Iadd.mode.Iaddend..
 17. The semiconductor memory .[.device.]. asclaimed in claim 16, wherein said .[.second.]. .Iadd.sixth.Iaddend.control circuit comprises:a .[.first.]. .Iadd.third.Iaddend.inverting circuit which inverts the .[.first.]. .Iadd.second.Iaddend.signal; a .[.first.]. .Iadd.second .Iaddend.NOR circuit which.[.performs a NOR operation on.]. .Iadd.receives .Iaddend.an outputsignal of the .[.first.]. .Iadd.third .Iaddend.inverting circuit and the.[.second.]. .Iadd.third .Iaddend.signal; and a .[.first.]. .Iadd.third.Iaddend.delay circuit which delays an output signal of the .[.first.]..Iadd.second .Iaddend.NOR circuit.
 18. The semiconductor memory.[.device.]. as claimed in claim 6, further comprising a .[.second.]..Iadd.seventh .Iaddend.control circuit which delays the .[.first.]..Iadd.second .Iaddend.signal to generate .[.a third.]. .Iadd.the first.Iaddend.signal used to control .[.timings at which the column gate isselected and released from a selected state at respective timings.]..Iadd.the column gate.Iaddend., which are .[.common to.]. .Iadd.commonlyused in .Iaddend.the read .[.operation.]. .Iadd.mode .Iaddend.and thewrite .[.operation.]. .Iadd.mode.Iaddend..
 19. The semiconductor memory.[.device.]. as claimed in claim 2, further comprising:.Iadd.a columngate controlled by a first signal, and disposed between the first pairof data transmission lines and the sense amplifier;.Iaddend. .[.asecond.]. .Iadd.an eighth .Iaddend.control circuit which controlstimings at which .[.a column.]. .Iadd.the first signal .Iaddend.is.[.selected and released from a selected state.]. .Iadd.outputted to thecolumn gate .Iaddend.in the read and write .[.operations.]..Iadd.modes.Iaddend.; and a .[.third.]. .Iadd.ninth .Iaddend.controlcircuit which .[.controls timings at which the column gate is selectedand released from the selected state,.]. .Iadd.is coupled to the eighthcontrol circuit, for outputting the first signal.Iaddend.; wherein.[.the.]. .Iadd.an activation .Iaddend.timing .[.at which the columngate is selected.]. .Iadd.of the first signal .Iaddend.in the write.[.operation.]. .Iadd.mode .Iaddend.lags behind .[.the.]. .Iadd.anactivation .Iaddend.timing .[.at which.]. of the .[.column gate isselected.]. .Iadd.first signal .Iaddend.in the read .[.operation.]..Iadd.mode .Iaddend.and .[.the.]. .Iadd.an inactivation .Iaddend.timing.[.at which the column gate is released from the selected state.]..Iadd.of the first signal .Iaddend.in the read .[.operation.]..Iadd.mode .Iaddend.substantially coincides with .[.the.]. .Iadd.aninactivation .Iaddend.timing .[.at which the column gate is releasedfrom the selected state.]. .Iadd.of the first signal .Iaddend.in thewrite .[.operation.]. .Iadd.mode.Iaddend..
 20. The semiconductor memory.[.device.]. as claimed in claim 19, wherein the .[.second.]..Iadd.eighth .Iaddend.control circuit comprises:a .[.first.]..Iadd.fourth .Iaddend.inverting circuit which inverts a .[.first.]..Iadd.second .Iaddend.signal defining an operation timing: a .[.first.]..Iadd.second .Iaddend.inverting delay circuit which inverts and delaysan output signal of the .[.first.]. .Iadd.fourth .Iaddend.invertingcircuit; a .[.first.]. .Iadd.fourth .Iaddend.NAND circuit which.[.performs a NAND operation on.]. .Iadd.receives .Iaddend.a.[.second.]. .Iadd.third .Iaddend.signal indicating .[.whether anoperation mode of the semiconductor memory device is.]. the write.[.operation.]. .Iadd.mode .Iaddend.or the read .[.operation.]..Iadd.mode .Iaddend.and .[.an.]. .Iadd.the .Iaddend.output signal of the.[.first.]. .Iadd.fourth .Iaddend.inverting circuit; and a .[.first.]..Iadd.fourth .Iaddend.delay circuit which delays an output signal of the.[.first.]. .Iadd.fourth .Iaddend.NAND circuit; and wherein the.[.third.]. .Iadd.ninth .Iaddend.control circuit comprises: a.[.second.]. .Iadd.fifth .Iaddend.NAND circuit which .[.performs a NANDoperation on.]. .Iadd.receives .Iaddend.an output signal of the.[.first.]. .Iadd.second .Iaddend.inverting delay circuit and an outputsignal of the .[.first.]. .Iadd.fourth .Iaddend.delay circuit; and a.[.second.]. .Iadd.fifth .Iaddend.inverting circuit which inverts anoutput signal of the .[.second.]. .Iadd.fifth .Iaddend.NAND circuit. 21.The semiconductor memory .[.device.]. as claimed in claim 2, furthercomprising:.Iadd.a column gate controlled by a first signal, anddisposed between the first pair of data transmission lines and the senseamplifier;.Iaddend. a .[.second.]. .Iadd.tenth .Iaddend.control circuitwhich controls timings at which .[.a column.]. .Iadd.the first signal.Iaddend.is .[.selected and released from a selected state.]..Iadd.outputting to the column gate .Iaddend.in the read .[.operation.]..Iadd.mode.Iaddend.; .[.a third.]. .Iadd.an eleventh .Iaddend.controlcircuit which controls timing at which .[.a column is selected andreleased from the selected state.]. .Iadd.the first signal is outputtedto the column gate .Iaddend.in the write .[.operation.]..Iadd.mode.Iaddend.; a .[.fourth.]. .Iadd.twelfth .Iaddend.controlcircuit which generates .[., from.]. .Iadd.the first signal in responseto .Iaddend.output signals of the .[.second.]. .Iadd.tenth .Iaddend.and.[.third.]. .Iadd.eleventh .Iaddend.control circuits .[., a third signalwhich controls timings at which the column gate is selected and releasedfrom the selected state.].; and a .[.fifth.]. .Iadd.thirteenth.Iaddend.control circuit which controls the .[.second.]. .Iadd.tenth.Iaddend.control circuit, wherein .[.the.]. .Iadd.an activation and aninactivation .Iaddend.timings .[.at which the column gate is selectedand released from the selected state.]. .Iadd.of the first signal.Iaddend.in the write .[.operation.]. .Iadd.mode .Iaddend.lag behind the.[.timings at which the column gate is selected and released from theselected state.]. .Iadd.activation and the inactivation of the firstsignal .Iaddend.in the read .[.operation.]. .Iadd.mode,respectively..Iaddend.
 22. The semiconductor memory .[.device.]. asclaimed in claim 21 wherein said .[.second.]. .Iadd.tenth.Iaddend.control circuit comprises:a .[.first.]. .Iadd.sixth.Iaddend.inverting circuit which inverts a .[.first.]. .Iadd.second.Iaddend.signal defining an operation timing; a .[.first.]. .Iadd.sixth.Iaddend.NAND circuit which .[.performs a NAND operation on.]..Iadd.receives .Iaddend.an output signal of the .[.first.]. .Iadd.sixth.Iaddend.inverting circuit and an output signal of the .[.fifth.]..Iadd.thirteenth .Iaddend.control circuit; and a .[.first.]. .Iadd.fifth.Iaddend.delay which delays an output signal of the .[.first.]..Iadd.sixth .Iaddend.NAND circuit, wherein said .[.third.]..Iadd.eleventh .Iaddend.control circuit comprises: a .[.second.]..Iadd.seventh .Iaddend.NAND circuit which .[.performs a NAND operationon.]. .Iadd.receives .Iaddend.a .[.second.]. .Iadd.third .Iaddend.signalindicating .[.whether an operation mode of the semiconductor memorydevice is.]. the write .[.operation.]. .Iadd.mode .Iaddend.or the read.[.operation.]. .Iadd.mode .Iaddend.and an output signal of the.[.first.]. .Iadd.sixth .Iaddend.inverting circuit; and a .[.second.]..Iadd.sixth .Iaddend.delay circuit which delays an output signal of the.[.second.]. .Iadd.seventh .Iaddend.NAND circuit, wherein said.[.fourth.]. .Iadd.twelfth .Iaddend. control circuit comprises: .[.athird.]. .Iadd.an eighth .Iaddend.NAND circuit which .[.performs a NANDoperation on.]. .Iadd.receives .Iaddend.output signals of the.[.second.]. .Iadd.tenth .Iaddend.and .[.third.]. .Iadd.eleventh.Iaddend.control circuits; and a .[.second.]. .Iadd.seventh.Iaddend.inverting circuit which inverts an output signal of the.[.third.]. .Iadd.eighth .Iaddend.NAND circuit, and wherein said.[.fifth.]. .Iadd.thirteenth .Iaddend.control circuit comprises: a.[.third.]. .Iadd.seventh .Iaddend.delay circuit which delays the.[.second.]. .Iadd.third .Iaddend.signal; and a .[.fourth.]. .Iadd.ninth.Iaddend.NAND circuit which .[.performs a NAND operation on.]..Iadd.receives .Iaddend.an output signal of the .[.third.]..Iadd.seventh .Iaddend.delay circuit and the .[.second.]. .Iadd.third.Iaddend.signal. .Iadd.
 23. A semiconductor memory having a read modeand a write mode, comprising:a sense amplifier; a pair of datatransmission lines for coupling the sense amplifier and a read circuitor a write circuit; a shortcircuit switch for shortcircuiting the pairof data transmission lines; a control circuit receiving a control signalwhich indicates the read mode or the write mode, for controlling anoperation of the shortcircuit switch in response to the control signal;wherein an OFF timing of the shortcircuit switch in the write mode isdifferent from that in the read mode..Iaddend..Iadd.24. Thesemiconductor memory as claimed in claim 23, wherein the OFF timing ofthe shortcircuit switch in the write mode is earlier than that in theread mode..Iaddend..Iadd.25. The semiconductor memory as claimed inclaim 24, the pair of data transmission lines including: a first pair ofdata transmission lines coupled to the sense amplifier; and a secondpair of data transmission lines coupled between the first pair of datatransmission lines and the write circuit; wherein the shortcircuitswitch is disposed between the second pair of data transmissionlines..Iaddend..Iadd.26. The semiconductor memory as claimed in claim25, wherein the shortcircuit switch is disposed in vicinity of the writecircuit..Iaddend..Iadd.27. The semiconductor memory as claimed in claim25, further comprising: a precharge circuit for supplying a prechargevoltage to the second pair of data transmission lines..Iaddend..Iadd.28.The semiconductor memory as claimed in claim 27, whereinthe prechargecircuit supplies the precharge voltage to the second pair of datatransmission lines while the second pair of data transmission lines isbeing shortcircuited, and does not supply the precharge voltage theretowhen the second pair of data transmission lines is notshortcircuited..Iaddend..Iadd.29. The semiconductor memory as claimed inclaim 27, wherein the control circuit turns the shortcircuit switch OFFbefore both of the second pair of data transmission lines complete to beprecharged to the precharge voltage, in the writemode..Iaddend..Iadd.30. The semiconductor memory as claimed in claim 27,wherein the control circuit turns the shortcircuit switch OFF after bothof the second pair of data transmission lines completes to be prechargedto the precharge voltage, in the read mode..Iaddend..Iadd.31. Thesemiconductor memory as claimed in claim 23, further comprising: acolumn gate controlled by a column selection signal, for coupling thesense amplifier and the pair of data transmission lines; wherein the OFFtiming of the shortcircuit switch in the read mode is substantially sameas an activation timing of the column selection signal, and an ON timingof the shortcircuit switch in the read mode is substantially same as aninactivation timing of the column selection signal..Iaddend..Iadd.32.The semiconductor memory as claimed in claim 23, further comprising: acolumn gate controlled by a column selection signal, for coupling thesense amplifier and the pair of data transmission lines; wherein the OFFtiming of the shortcircuit switch in the write mode is earlier than anactivation timing of the column selection signal..Iaddend..Iadd.33. Thesemiconductor memory as claimed in claim 32, whereinthe OFF timing ofthe shortcircuit switch in the write mode is substantially same as anactivation timing of the write circuit..Iaddend..Iadd.34. Thesemiconductor memory as claimed in claim 23, further comprising: acolumn gate controlled by a column selection signal, for coupling thesense amplifier and the pair of data transmission lines; wherein anactivation timing of the column selection signal in the read mode isearlier than that in the write mode..Iaddend..Iadd.35. The semiconductormemory as claimed in claim 34, wherein an inactivation timing of thecolumn selection signal in the read mode is earlier than that in thewrite mode..Iaddend..Iadd.36. A method of controlling data transmissionlines of a semiconductor memory having a read mode and a write mode,including a pair of data transmission for coupling a sense amplifier anda read circuit or a write circuit and a shortcircuit switch forshortcircuiting the pair of data transmission lines; said methodcomprising: a) turning the shortcircuit switch OFF at a first timing inthe read mode; b) turning the shortcircuit switch OFF at a second timingin the write mode, the second timing being earlier than the firsttiming..Iaddend..Iadd.37. A semiconductor memory having a read mode anda write mode, comprising: a sense amplifier; a pair of data transmissionlines for coupling the sense amplifier and a read circuit or a writecircuit; a shortcircuit switch for shortcircuiting the pair of datatransmission lines; a control circuit receiving a control signal whichindicates the read mode or the write mode, for controlling an operationof the shortcircuit switch in response to the control signal; aprecharge circuit for supplying a precharge voltage to the pair of datatransmission lines; wherein an OFF timing of the shortcircuit switch inthe write mode is earlier than a precharge completion timing of the pairof data transmission lines..Iaddend..Iadd.38. The semiconductor memoryas claimed in claim 37, wherein the OFF timing of the shortcircuitswitch is substantially same timing as an activation timing of the writecircuit..Iaddend..Iadd.39. A semiconductor memory having a read mode anda write mode, comprising:a sense amplifier; a pair of data transmissionlines for coupling the sense amplifier and a read circuit or a writecircuit; a shortcircuit switch receiving a shortcircuit signal forshortcircuiting the pair of data transmission lines; and a controlcircuit receiving a timing signal and a control signal which indicatesthe read mode or the write mode, for outputting the shortcircuit signalin response to the timing signal and the control signal, wherein thecontrol circuit includes: a first part receiving the timing signal andthe control signal for outputting a second timing signal to control anoutput timing of the shortcircuit signal in the write mode; and a secondpart receiving the timing signal for outputting a third timing signal tocontrol the output timing of the shortcircuit in the readmode..Iaddend..Iadd.40. The semiconductor memory as claimed in claim 39,wherein an OFF timing of the shortcircuit switch in the write mode isearlier than that in the read mode..Iaddend..Iadd.41. The semiconductormemory as claimed in claim 39, wherein a first delay time in the writemode produced by the first part is shorter than a second delay time inthe read mode produced by the second part..Iaddend..Iadd.42. Thesemiconductor memory as claimed in claim 39, the pair of datatransmission lines including: a first pair of data transmission linescoupled to the sense amplifier; and a second pair of data transmissionlines coupled between the first pair of data transmission lines and thewrite circuit; wherein the shortcircuit switch is disposed between thesecond pair of data transmission lines..Iaddend..Iadd.43. Thesemiconductor memory as claimed in claim 42, further comprising: aprecharge circuit for supplying a precharge voltage to the second pairof data transmission lines..Iaddend..Iadd.44. The semiconductor memoryas claimed in claim 43, wherein the precharge circuit supplies theprecharge voltage to the second pair of data transmission lines whilethe second pair of data transmission lines is being shortcircuited, anddoes not supply the precharge voltage thereto when the second pair ofdata transmission lines is not shortcircuited..Iaddend..Iadd.45. Thesemiconductor memory as claimed in claim 44, whereinthe control circuitturns the shortcircuit switch OFF before each lines of the second pairof data transmission lines completes to be precharged to the prechargevoltage, in the write mode..Iaddend..Iadd.46. The semiconductor memoryas claimed in claim 44, wherein the control circuit turns theshortcircuit switch OFF after each line of the second pair of datatransmission lines completes to be precharged to the precharge voltage,in the read mode..Iaddend..Iadd.47. The semiconductor memory as claimedin claim 40, wherein the OFF timing of the shortcircuit switch in thewrite mode is substantially same as an activation timing of the writecircuit..Iaddend.